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FRACTIONAL-N RF/INTEGER-N IF DUAL PLL
S1M8836/37
INTRODUCTION
The S1M8836/37 is a Fractional-N frequency synthesizer with integrated prescalers, designed for RF operation up to 1.0GHz/2.5GHz and for IF operation up to 520MHz. The fractional-N synthesizer allows fast-locking, low phase noise phase-locked loops to be built easily, thus having rapid channel switching and reducing standby time for extended battery life. The S1M8836/37 based on - fractional-N techniques solves the fractional spur problems in other fractional-N synthesizers based on charge pump compensation. The synthesizer also has an additional feature that the PCS/CDMA channel frequency in steps of 10kHz can be accurately programmed.
24-QFN-3.5x4.5
The S1M8836/37 contains quadruple-modulus prescalers. The S1M8836 RF synthesizer adopts an 8/9/12/13 prescaler(16/17/20/21 for the S1M8837) and the IF synthesizer adopts an 8/9 prescaler. Phase detector gain is user-programmable for maximum flexibility to address IS-95 CDMA and IMT2000. Various program-controlled power down options as well as low supply voltage help the design of wireless cell phones having minimum power consumption. Using the Samsung's proprietary digital phase-locked-loop technique, the S1M8836/37 has a linear phase detector characteristic and can be used for very stable, low noise PLL's. Supply voltage can range from 2.7V to 4.0V. The S1M8836/37 is available in a 24-QFN package.
FEATURES
* * * * * High operating frequency dual synthesizer Operating voltage range : 2.7 to 4.0V Low current consumption(S1M8836: 5.5mA, S1M8837: 7.5mA) Selectable power saving mode (Icc = 1uA typical @3V) Quadruple-modulus prescaler and Fractional-N/Integer-N: S1M8836 S1M8837 S1M8836/37 * * * * * * * * (RF) 8/9/12/13 (RF) 16/17/20/21 (IF) 8/9 Fractional-N Fractional-N Integer-N
S1M8836: 250MHz to 1.0GHz(RF) / 45MHz to 520MHz(IF) S1M8837: 500MHz to 2.5GHz(RF) / 45MHz to 520MHz(IF) Excellent in-band phase noise ( - 85dBc/Hz @ PCS, - 90dBc/Hz @ CDMA) Improved fractional spurious performance ( < 80dBc ) Frequency resolution (= 10kHz/64 @ fref = 9.84MHz) Fast channel switching time: <500us Programmable charge pump output current: from 50A to 800A in 50A steps Programmability via on-chip serial bus interface
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S1M8836/37
FRACTIONAL-N RF/INTEGER-N IF DUAL PLL
APPLICATIONS
* * * High-rate data-service cellular telephones (for CDMA) : S1M8836, S1M8837 High-rate data-service portable wireless communications : S1M8837 Other wireless communications systems
ORDERING INFORMATION
Device + S1M8836X01-G0T0 + S1M8837X01-G0T0 +: New Product Package 24-QFN-3.5x4.5 Operating Temperature -40 to +85C
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FRACTIONAL-N RF/INTEGER-N IF DUAL PLL
S1M8836/37
BLOCK DIAGRAM
OUT0 24
OUT1 23
VDDIF 22
VDDRF
1 RF LD 2 RF Charge Pump RF Phase Detector IF Phase Detector IF Charge Pump 20 CPOIF RF Prescaler IF Prescaler
-+
foLD Data Out Multiplexer
IF LD 21 VPIF
VPRF
CPORF
3
DGND
4
+-
19 DGND
Prescaler Control fin RF 5
RF Programmable Counter
IF Programmable Counter
Prescaler Control 18 finIF
fin RF
6 RF N-Latch IF N-Latch 2-Bit Control
17 finIF
GNDRF
7
Frac-N Latch & - Modulator
20-Bit Shift Register
16 GNDIF
VDDRFa
8
RF R-Latch
IF R-Latch
15 LE
OSCin
9
RF Reference Counter
IF Reference Counter
14 DATA
13 CLOCK 10 foLD 11 RF_EN 12 IF_EN
3
S1M8836/37
FRACTIONAL-N RF/INTEGER-N IF DUAL PLL
PIN DIAGRAM
OUT0 24 VDDRF 1
OUT1 23
VDDIF 22 21 VPIF
VPRF
2
20 CPOIF
CPORF
3
19 DGND
DGND
4
18 finIF 17 finIF 16 GNDIF
finRF finRF
5
S1M8836/37
6
GNDRF
7
15 LE
VDDRFa
8
14 DATA
OSCin
9 10 foLD 11 RF_EN 24-QFN 12 IF_EN
13 CLCOK
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FRACTIONAL-N RF/INTEGER-N IF DUAL PLL
S1M8836/37
PIN DESCRIPTION
Pin No. 1 2 3 4 5 6 7 8 9 10 11 Symbol VDDRF VpRF CPoRF DGND finRF finRF GNDRF VDDRFa OSCin foLD RF_EN - - I O I I/O - - O - I I Descriptions RF PLL power supply (2.7V to 4.0V). Must be equal to VDDIF. Power supply for RF charge pump. Must be VDDRF and VDDIF. RF charge pump output. Connected to an external loop filter. Ground for RF PLL digital circuitry. RF prescaler input. Small signal input from the external VCO. RF prescaler complementary input. For a single-ended output RF VCO, a bypass capacitor should be placed as close as possible to this pin and be connected directly to the ground plane. Ground for RF PLL analog circuitry. PLL power supply (2.7V to 4.0V) for RF analog (prescaler). Must be equal to VDDRF Oscillator input to drive both the IF and RF R counter inputs. Multiplexed output of N or R divider and RF/IF lock detect. RF PLL Enable (Enable when HIGH, Power down when LOW). Controls the RF PLL to power down directly, not depending on a program control. Also sets the charge pump output to be in TRI-STATE when LOW. Powers up when HIGH depends on the state of RF_CTL_WORD. IF PLL Enable (Enable when HIGH, Power-down when LOW). Controls the IF PLL to power down directly. The same as RF_EN except that power-up depends on the state of IF_CTL_WORD. CMOS clock input. Data for the various counters is clocked into the 22-bit shift register on the rising edge. Binary serial data input. Data entered MSB (Most Significant Bit) first. Load enable when LE goes HIGH. High impedance CMOS input. Ground for IF analog circuitry. IF prescaler complementary input. For a single-ended output IF VCO, a bypass capacitor should be placed as close as possible to this pin. IF prescaler input. Small signal input from the VCO. Ground for IF PLL digital circuitry. IF charge pump output. Connected to an external loop filter. Power supply for IF charge pump. Must be VDDRF and VDDIF. IF PLL power supply (2.7V to 4.0V). Must be equal to VDDRF. Programmable CMOS output. Level of the output is controlled by W2[19] bit. Programmable CMOS output. Level of the output is controlled by W2[18] bit. In the Speedy Lock mode, the OUT0 and OUT1 pins can be utilized as synchronous switches between active low and tri-state.
12
IF_EN
I
13 14 15 16 17 18 19 20 21 22 23 24
CLOCK DATA LE GNDIF finIF finIF DGND CPoIF VpIF VDDIF OUT1 OUT0
I I I - I I - O - - O O
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FRACTIONAL-N RF/INTEGER-N IF DUAL PLL
S1M8836/37
EQUIVALENT CIRCUIT DIAGRAM
CLOCK, DATA, LE
foLD
OSCin
CPORF, CPOIF
finRF, finRF, finIF, finIF
finRF, finIF
finRF, finIF
Vbias
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FRACTIONAL-N RF/INTEGER-N IF DUAL PLL
S1M8836/37
ABSOLUTE MAXIMUM RATINGS Characteristics Power supply voltage Voltage on any pin with GND = 0 volts Power dissipation Operating temperature Storage temperature Symbol VDD VI PD Ta TSTG Value 0.0 to 4.0 -0.3 to VDD + 0.3 600 -40 to +85 -65 to +150 Unit V V mW C C
ELECTROSTATIC CHARACTERISTICS Characteristics Human Body Model Machine Model Charge Device Model Pin No. All All All ESD level < 2000 < 300 < 800 Unit V V V
NOTE: These devices are ESD sensitive. These devices must be handled in an ESD protected environment.
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S1M8836/37
FRACTIONAL-N RF/INTEGER-N IF DUAL PLL
ELECTRICAL CHARACTERISTICS (VDD=3.0V, Vp=3.0V, Ta = 25C, unless otherwise specified.) Characteristic Power supply voltage Symbol VDD VP Power supply current S1M8836 RF+IF S1M8837 RF+IF S1M8836 RF+IF S1M8837 RF+IF IF only Power down current IPWDN VIH VIL IIH IIL VDD=3.0V VDD=2.7V to 4.0V VDD=2.7V to 4.0V VIH=VDD=4.0V VIL=0V, VDD=4.0V -1.0 -1.0 0.7VD
D
Test Conditions
Min. 2.7 VDD
Typ. 3.0 3.0 5.5 7.5 4.0 6.0 1.5 1
Max. 4.0 4.0
Unit V
IDD
Fractional-N mode (fosc=19.68MHz, RF R=2) Quiescent State
mA
10
A V
Digital Inputs: CLOCK, DATA and LE High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current Reference Oscillator Input: OSCin Input Current IIHR IILR Digital Output: foLD High Level Output Voltage Low Level Output Voltage VOH VOL Iout=-500A Iout=+500A VDD-0.4 0.4 V V VIH=VDD=4.0V VIL=0V, VDD=4.0V -100 +100 A A
0.3VD
D
V A A
+1.0 +1.0
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FRACTIONAL-N RF/INTEGER-N IF DUAL PLL
S1M8836/37
ELECTRICAL CHARACTERISTICS (Continued) (VDD=3.0V, Vp=3.0V, Ta = 25C, unless otherwise specified.) Characteristic Symbol Charge Pump Outputs: CPoRF, CPoIF RF Charge Pump Output Current ICPRF
SOURCE_min
Test Conditions VCP=VP/2, RF_CP_WORD=0000 VCP=VP/2, RF_CP_WORD=0000 VCP=VP/2, RF_CP_WORD=1111 VCP=VP/2, RF_CP_WORD=1111 VCP=VP/2,CP_GAIN_8=0 VCP=VP/2,CP_GAIN_8=0 VCP=VP/2,CP_GAIN_8=1 VCP=VP/2,CP_GAIN_8=1 0.5V VCP VP-0.5V VCP=VP/2 0.5V VCP VP-0.5V VCP=VP/2
Min.
Typ. -50 +50 -800 +800 -100 +100 -800 +800
Max.
Unit A A A A A A A A
ICPRFSINK_min
ICPRFSOURCE_max
ICPRFSINK_max
IF Charge Pump Output Current
ICPRF
SOURCE_min
ICPRF
SINK_min
ICPRF
SOURCE_max
ICPRF
SINK_max
Charge Pump Leakage Current Sink vs. Source Mismatch Output Current Magnitude Variations. Voltage Output Current vs. Temperature
ICPL ICP-SINK vs ICP-SOURCE ICP VS VCP ICP VS Ta
-2.5 3 10 10 0.5 0.25 45 2
+2.5 10 15
nA % % %
Operating Frequency, Input Sensitivity (Programmable Divider, PFD) f inRF RF Operating S1M8837 Fractional-N mode (fosc=19.68MHz, RF R=2) Frequency S1M8836 IF Operating Frequency Reference Oscillator Input Frequency Phase Detector Operating Frequency RF Input Sensitivity IF Input Sensitivity Reference Oscillator Input Sensitivity f inIF OSCin f PD PfinRF PfinIF VOSCin VDD=3.0V VDD=4.0V VDD=2.7V to 4.0V Fractional-N mode (fosc=19.68MHz, RF R=2) VDD=3.0V
2.5 1.0 520 40 10
GHz GHz
MHz MHz MHz dBm dBm dBm VPP
-15 -10 -10 0.5
0 0 0 VDD
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S1M8836/37
FRACTIONAL-N RF/INTEGER-N IF DUAL PLL
ELECTRICAL CHARACTERISTICS (Continued) (VDD=3.0V, Vp=3.0V, Ta = 25C, unless otherwise specified.) Characteristic Serial Data Control CLOCK Frequency CLOCK Pulse Width High CLOCK Pulse Width Low DATA Set Up Time to CLOCK Rising Edge DATA Hold Time after CLOCK Rising Edge LE Pulse Width CLOCK Rising Edge to LE Rising Edge f CLOCK tCWH tCWL tDS tDH tLEW tCLE 50 50 50 10 50 50 10 MHz ns ns ns ns ns ns Symbol Test Conditions Min. Typ. Max. Unit
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FRACTIONAL-N RF/INTEGER-N IF DUAL PLL
S1M8836/37
FUNCTIONAL DESCRIPTION
finRF finRF
+ -
RF Prescaler
RF N Counter
RF Phase Detector RF LD
RF Charge Pump
CPoRF
- Modulator
CLOCK DATA LE
Serial Data Control
CMOS Output MUX
OUT0
RF R Counter
foLD Data Out Multiplexer
foLD
OSC in
IF R Counter
CMOS Output MUX IF LD IF Phase Detector IF Charge Pump
OUT1
finIF finIF
+ -
IF Prescaler
IF N Counter
CPoIF
The Samsung S1M8836/37 is RF/IF dual frequency synthesizer IC which supports Fractional-N mode for RF PLL and Integer-N mode for IF PLL depending on a program control. S1M8836/37 combined with an external LPF and an external VCO forms PLL frequency synthesizer. The frequency synthesizer consists of prescalers, pulseswallowed programmable N counters, programmable reference R counters, phase detectors, programmable charge pumps, analog LD(lock detector), serial data control, etc. An input buffer in the prescaler amplifies the RF input power of -10dBm from the external RF/IF VCO to the sufficient ECL switching level to drive the following ECL divider so that it can be normally operated even in a smaller input power less than -10dBm. The amplified VCO output signal is divided by the prescaler with a predetermined divide ratio (div. 8/9/12/13 for S1M8836, div. 16/17/20/21 for S1M8837, div. 8/9 for IF), the N counter and the Fractional-N circuitry( - modulator). External reference signal is divided by the R counter to set the comparison frequency of the PFD. The divide ratios of the programmable counters can be programmed via the serial bus interface. These two signals drive the both inputs of the phase detector. The phase detector drives the charge pump by comparing frequencies and phases of the above two signals. The charge pump and the external LPF make the control voltage for the external VCO and finally the VCO generates the appropriate frequency signal.
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S1M8836/37
FRACTIONAL-N RF/INTEGER-N IF DUAL PLL
When the PLL is in the locked state, the RF VCO's frequency will be NINT + NFRAC times the comparison frequency, where NINT is the integer divide ratio and NFRAC is the fractional component. The S1M8836/37 has new improved features compared to conventional Integer-N PLLs. The fractional-N PLL is available for the RF. The fractional synthesis frequency as is AMPS and IS-95A/B/C. This makes it possible to widen the loop bandwidth as wide as 20kHz or wider for a faster lock-up time and to improve the in-band phase noise performance due to the reduced divide ratio N. Such S1M8836/37 in the fractional-N mode is suitable for CDMA, GSM and PCS band applications. Also, from the programmability of the charge pump, the users can easily design a stable loop by free selection of loop components and reach to the low spurious, the low power PLL by an optimized current selection. Prescaler The RF/IF prescaler consists of a differential input buffer and ECL frequency dividers. The input buffer amplifies the input signal from the external VCO to the required level set by sensitivity requirements. The output of the amplifier delivers a differential signal to the divider with the correct DC level. The buffer may be either singleended or differentially driven. The single-ended operation is preferred in typical applications due to external VCO. In this case, we recommend that the complementary input /fin of the input buffer be AC coupled to ground through external capacitors, even though it is internally coupled to ground via an internal 10pF capacitor. The other input pin fin of the buffer also needs external capacitor for decoupling the DC component and controlling the input power level. The RF prescalers of S1M8836 and S1M8837 provide 8/9/12/13 and 16/17/20/21 prescaler ratio, respectively. The IF prescaler of S1M8836/37 contains 8/9 dual modulus prescaler. Reference Oscillator Inputs The reference oscillator frequency is provided by an external reference such as TCXO through the OSCin. It drives both the IF R and RF R counters. Programmable Dividers (RF/IF N Counters) The RF N counter can be configured as a fractional counter. The fractional-N counter is selected when the Frac-N_SEL bit becomes HIGH. In the fractional mode, the S1M8836 is capable of offering a continuous integer divide range from 25 to 1023 and the S1M8837 offering a continuous integer divide range from 49 to 2047. The S1M8836/37 IF N counter supports an integer counter mode only, not including fractional counter, and is capable of operating from 45MHz to 520MHz offering a continuous integer divide range from 72 to 32767.
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FRACTIONAL-N RF/INTEGER-N IF DUAL PLL
S1M8836/37
- modulator The RF part of S1M8836/37 adopts the - modulator as a core of the fractional counter that makes it possible to obtain divide ratio N to be a fractional number between two contiguous integers. The - modulator effectively randomizes the quantization noise generated from digitizing process and results in extreme suppression of in-band noise power by pushing it out to out-of-band as in conventional - data converter. This technique eliminates the need for compensation current injection into the loop filter and improves fractional spurious performance, suitable for high-tier applications. The - modulator operates only for fractional-N mode, when the Frac-N_SEL is HIGH. For proper use of the fractional mode, the user should be kept in mind that 1. A fractional number should be set in the range from -0.5 to 0.5 in step of 1/62976. 2. For S1M8836/7, R can be selected 1-3. The clock frequency fixed at 9.84MHz (=19.68MHz/2, R=2) is recommended for the - modulator which is an optimum condition for achieving good electrical performances related to the fractional noise and power consumption. Only when using this clock frequency, the S1M8836/37 guarantees the exact frequency resolutions: 10kHz for CDMA PCS and 30kHz for CDMA cellular. Note that the clock frequency much lower than 9.84MHz can deteriorate the fractional noise performance. Users can use R=1 or R=3, too. For the case of R=1 or R=3, users must ask SAMSUNG for details. Fractional noise performance may become better for R=1 (clock frequency=19.68MHz/1=19.68MHz). But the RF operating frequency range may be shrinked for that case of R=1. Phase-Frequency Detector (PFD) and Charge Pump (CP) The RF/IF phase detector composed of PFD and CP outputs pump current into an external loop filter in proportional to the phase difference between outputs of N and R counter. The phase detector has a better linear transfer characteristic due to a feedback loop to eliminate dead zone. The polarity of the PFD can be programmed using RF_PFD_POL/IF_PFD_POL depending on whether RF/IF VCO characteristics are positive or negative. (Programmable descriptions for phase detection polarity) Power-Down(or Power-Save) Control Each PLL is individually power controlled by the enable pins (RF_EN and IF_EN pins) or program control bits (PWDN, PWDN_RF/IF). The enable pins override the program control bits. When both enable pins are HIGH, the program control bits determine the state of power control. Power down forces all the internal blocks to be deactivated and the charge pump output to be in the TRISTATE. The control register, however, remains active for serial programming and is capable of loading and latching in data during the power down.
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S1M8836/37
FRACTIONAL-N RF/INTEGER-N IF DUAL PLL
Programming Description The S1M8836/37 can be programmed via the serial bus interface. The interface is made of 3 functional signals: clock, data, and latch enable(LE). Serial data is moved into the 22-bit shift register on the rising edge of the clock. These data enters MSB first. When LE goes HIGH, data in the shift register is moved into one of the 4 latches (by the 2-bit control).
MSB
Data Flow (MSB First) DATA[21:2]
LSB CTL[1:0]
Control Bit Map (CTL[1:0]) Control Bits CTL2(CTL[1]) 0 0 1 1 CTL1(CTL[0]) 0 1 0 1 WORD1 WORD2 WORD3 WORD4 DATA Location
Data Bit Map (DATA[21:2]) First Bit WORD1(W1) WORD2(W2) WORD3(W3) IF_CTL_ WORD CMOS RF_R (2Bit) IF_CP_ WORD RF_CP_WORD REGISTER BIT LOCATION 9 8 7 6 5 4 3 2 IF _R_CNTR(15Bit) IF_NB_CNTR(12Bit) RF_NB_CNTR(7Bit) IF_NA_ CNTR(3Bit) RF_NA_CNTR (36:3Bit) RF_NA_CNTR (37:4Bit) WORD4(W4) RF_CTL_ WORD FRAC_CNTR(17Bit) 11 Last Bit 1 0 00 01 10
21 20 19 18 17 16 15 14 13 12 11 10
FoLD(4Bit)
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FRACTIONAL-N RF/INTEGER-N IF DUAL PLL
S1M8836/37
Data Bit Map (DATA[21:2]) (Continued) Control Words IF_CTL_WORD Control bits W1[21] W1[20] W1[19] CMOS W2[21] W2[20] W2[19] IF_CP_WORD W2[18] W2[17] foLD W3[21:18] Acronym IF_CNT_RST PWDN_IF PWDN Speedy_Lock OUT1 OUT0 IF_CP_GAIN IF_PFD_POL foLD LOW (0) normal operation power up asynchronous power down CMOS output voltage LOW voltage LOW 1X negative slope HIGH (1) IF counter reset power down synchronous power down Speedy_Lock mode voltage HIGH voltage HIGH 8X positive slope pin #23 pin #24 IF charge pump IF PFD Lock Detector(LD), Test mode RF charge pump RF PFD RF RF RF; PLL mode selection IF IF RF and IF Comments
select LDs and monitoring mode of internal counters. (FoLD control for control codes in detail) select 16-level charge pump current (RF charge pump gain for control codes in detail) negative slope normal operation power up Integer-N mode positive slope RF counter reset power down Fractional-N mode
RF_CP_WORD
W3[17:14]
RF_CP_LVL
W3[13] RF_CTL_WORD W4[21] W4[20] W4[19]
RF_PFD_POL RF_CNT_RST PWDN_RF Frac-N_SEL
-- Counter Reset mode resets R & N counters. -- IF charge pump current can be selected to high current(8X) or low current(1X) mode. -- In the Speedy_Lock mode, the OUT0 and OUT1 pins can be utilized as synchronous switches between active low and tri-state. The Speedy_Lock mode activates the OUT0 and OUT1 pins to be connected to GROUND with a low impedance(< 150) while a high charge pump gain( 8X) is selected and otherwise to the TRISTATE. -- For using a programmable CMOS output, the CMOS output bit(W2[21]=L) should be activated and then the desired logic level should be programmed with the control bits W2[19] for OUT0 and W2[20] for OUT1.
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S1M8836/37
FRACTIONAL-N RF/INTEGER-N IF DUAL PLL
Programmable Reference Counter(W1[18:2]) If the Control Bit is 00, data is moved from the 22-bit shift register into the R-latch which sets the IF reference counter. Serial data format is shown in the table below.
MSB IF_CTL_WORD[21:19] 21 Program Code
W1[21:0] RF_R_CNTR[[18:17]: 1~3 19 18 Division Ratio of the RF R Counter,RF_R_CNTR 17 16 Division Ratio of the IF R Counter, IF_R_CNTR Control Bits IF_R_CNTR[16:2]: 3~32767 21 0
LSB 0 0
*
15-Bit IF R Counter Division Ratio
Division ratio : 3 to 32767(The divide ratios less than 3 are prohibited) Data are shifted in MSB first. Division Ratio 3 4 * 32767 * 14 0 0 * 1 13 0 0 * 1 12 0 0 * 1 11 0 0 * 1 10 0 0 * 1 9 0 0 * 1 8 0 0 * 1 7 0 0 * 1 6 0 0 * 1 5 0 0 * 1 4 0 0 * 1 3 0 0 * 1 2 0 1 * 1 1 1 0 * 1 0 1 0 * 1
RF R Counter Division Ratio
Division ratio : 1 to 3 Division Ratio 1 1 2 3 1 0 0 1 1 0 0 1 0 1
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FRACTIONAL-N RF/INTEGER-N IF DUAL PLL
S1M8836/37
Programmable Counter(N Counter) If the Control Bits are 01(IF), 10, and 11(RF), data is transferred from the 22-bit shift register into the N/Fraclatch. N Counter consists of swallow counter(A counter; 3-bit for IF & S1M8836RF and 4-bit for S1M8837RF), main counter(B counter; 7-bit for S1M8836/37 RF and 12-bit for IF), and fractional counter(F counter; 17-bit for S1M8836/37 RF). Serial data format is shown below. IF N Counter
MSB CMOS 21 19 18 Program Code IF_CP_WORD [18:17] 17 16 Division Ratio of the IF N Counter Control Bits W2[21:0] IF_NB_CNTR[16:5] : 3 - 4095 IF_NA_CNTR[4:2] : 0-7 54 0 21 LSB 1 0
*
IF Main Counter Division Ratio(B Counter) IF_NB_ CNTR[16:5] ; for S1M8836/37 Division Ratio(B) 3 4 * 4095 11 0 0 * 1 10 0 0 * 1 9 0 0 * 1 8 0 0 * 1 7 0 0 * 1 6 0 0 * 1 5 0 0 * 1 4 0 0 * 1 3 0 0 * 1 2 0 1 * 1 1 1 0 * 1 0 1 0 * 1
Division ratio: 3 to 4095 (The division ratios less than 3 are prohibited)
*
Swallow Counter Division Ratio (A Counter) IF_NA_CNTR[4:2] ; for S1M8836/37 Division Ratio(A) 0 1 * 7 2 0 0 * 1 1 0 0 * 1 0 0 1 * 1
Division Ratio: 0 to 7, B>A
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S1M8836/37
FRACTIONAL-N RF/INTEGER-N IF DUAL PLL
RF N Counter
MSB FoLD[21:18] 21 RF_CP_WORD [17:13] 18 17 Program Code 13 12 Division Ratio of the RF N Counter Control Bits W3[21:0] RF_NB_CNTR[12:6] : 3 ~ 127 65 RF_NA_CNTR[5:2] 1 21 LSB 0 0
*
RF Main Counter Division Ratio (B Counter) RF_NB_ CNTR[12:6] ; for S1M8836/37 Division Ratio(B) 3 4 * 7 6 0 0 * 1 5 0 0 * 1 4 0 0 * 1 3 0 0 * 1 2 0 1 * 1 1 1 0 * 1 0 1 0 * 1
Division ratio : 3 to 127 (The division ratios less than 3 are prohibited)
*
RF Swallow Counter Division Ratio (A Counter) RF_NA_CNTR[5:2] ; for S1M8836 Division Ratio(A) 0 1 * 7 3 X X * X 2 0 0 * 1 1 0 0 * 1 0 0 1 * 1
Division Ratio : 0 to 7 X = Don't care condition
RF_NA_CNTR[5:2] ; for S1M8837 Division Ratio(A) 0 1 * 15
NOTE: Division Ratio: 0 to 15 X = Don't care condition
3 0 0 * 1
2 0 0 * 1
1 0 0 * 1
0 0 1 * 1
18
FRACTIONAL-N RF/INTEGER-N IF DUAL PLL
S1M8836/37
RF Fractional Counter
MSB RF_CTL_WORD[21:19] 21 Program Code 19 18 Division Ratio of the RF Fractional Counter Control Bits W4[21:0] FRAC_CNTR[18:2] 1 21 LSB 1 0
*
RF Fractional Counter Value (F Counter) FRAC_ CNTR[18:2] ; for S1M8836/37 RF Counter Value (F) 31488 * 2 1 0 -1 -2 * -31488 F 16 0 * 0 0 0 1 1 * 1 F 15 0 * 0 0 0 1 1 * 1 F 14 1 * 0 0 0 1 1 * 0 F 13 1 * 0 0 0 1 1 * 0 F 12 1 * 0 0 0 1 1 * 0 F 11 1 * 0 0 0 1 1 * 0 F 10 0 * 0 0 0 1 1 * 1 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0 1 * 0 0 0 1 1 * 0 1 * 0 0 0 1 1 * 1 0 * 0 0 0 1 1 * 0 0 * 0 0 0 1 1 * 0 0 * 0 0 0 1 1 * 0 0 * 0 0 0 1 1 * 0 0 * 0 0 0 1 1 * 0 0 * 0 0 0 1 1 * 0 0 * 1 0 0 1 1 * 0 0 * 0 1 0 1 0 * 0
F Counter Value: -31488(2's complementary) to 31488
NOTE: For a negative integer, the counter value should be inputted as the corresponding 2's complementary binary code. For instance, the 2's complementary binary code of -2 is 1 1111 1111 1111 1110.
19
S1M8836/37
FRACTIONAL-N RF/INTEGER-N IF DUAL PLL
Programmable PFD and Charge Pump IF Charge Pump Gain ( IF_CP_WORD; W2[18] ) Control Words IF_CP_WORD Control bits W2[18] Acronym IF_CP_GAIN LOW (0) 1x (100A) HIGH (1) 8x (800A) Comments IF charge pump
RF Charge Pump Gain ( RF_CP_WORD; W3[17:14] ) Control Words RF_CP_WORD Control bits W3[17:14] Acronym RF_CP_LVL LOW (0) HIGH (1) Comments RF charge pump
select 16-level charge pump current
Icpo (A) 50 100 * 200 250 * 400 450 * 800
8X W3[17] 0 0 * 0 0 * 0 1 * 1
4X W3[16] 0 0 * 0 1 * 1 0 * 1
2X W3[15] 0 0 * 1 0 * 1 0 * 1
1X W3[14] 0 1 * 1 0 * 1 0 * 1
Phase Detector Polarity ( RF_CP_WORD/IF_CP_WORD; W3[13]/W2[17] ) Depending on VCO characteristics, W2[17] and W3[13] bits should be set as follows : Control bits W2[17] W3[13] LOW (0) Negative Slope Negative Slope HIGH (1) Positive Slope Positive Slope Comments IF PFD RF PFD
20
FRACTIONAL-N RF/INTEGER-N IF DUAL PLL
S1M8836/37
VCO Characteristics (1)
VCO Output Frequency (2) VCO Input Voltage
Program Mode Control Power down mode operation Control Words IF_CTL_WORD Control bits W1[20] W1[19] RF_CTL_WORD W4[20] Acronym PWDN_IF PWDN PWDN_RF LOW (0) power up asynchronous power down power up HIGH (1) power down synchronous power down power down Comments IF RF and IF RF
Each PLL is individually power controlled by the enable pins (RF_EN and IF_EN pins) or program control bits (PWDN, PWDN_RF/IF). The enable pins override the program control bits. When both enable pins are HIGH, the program control bits determine the state of power control. Power down forces all the internal analog blocks to be deactivated and the charge pump output to be in a TRISTATE. The oscillator buffer is powered down when the power down bits (W4[20] and W1[20]) become HIGH. The control register and R/N counters, however, remains active for permitting serial programming and is capable of loading and latching in data during the power down. There are synchronous and asynchronous power-down modes for S1M8836/37. The power-down bit W1[19] is used to select between synchronous and asynchronous power-down. Synchronous power-down mode occurs if W1[19] bit is HIGH and then the power down bit (W4[20] or W1[20]) becomes HIGH. In the synchronous power down mode, the power-down function will go into power-down mode upon the completion of a charge pump pulse event because it is synchronized with the charge pump and thus can diminish undesired frequency jumps. Asynchronous power down mode occurs if W1[19] bit is LOW and then the power down bit (W4[20] or W1[20]) becomes HIGH. Activation of the asynchronous function will go into power-down mode immediately. RF Power down mode table W4[20] 0 0 1 1 W1[19] 0 1 1 1 RF PLL active RF PLL active, only charge pump to TRISTATE Asynchronous power down Synchronous power down Power down mode status
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S1M8836/37
FRACTIONAL-N RF/INTEGER-N IF DUAL PLL
IF Power down mode table W1[20] 0 0 1 1 W1[19] 0 1 0 1 IF PLL active IF PLL active, only charge pump to TRISTATE Asynchronous power down Synchronous power down Power down mode status
Programmable Counter Reset Control Control Words IF_CTL_WORD RF_CTL_WORD Control bits W1[21] W4[21] Acronym IF_CNT_RST RF_CNT_RST LOW (0) normal operation HIGH (1) IF counter reset Comments IF RF
normal operation RF counter reset
Counter Reset mode resets R & N counters.
RF Fractional-N selection Control Words RF_CTL_WORD Control bits W4[19] Acronym Frac_N_SEL LOW (0) reserved HIGH (1) Fractional-N mode Comments RF;PLL mode selection
CMOS Output Control Control Words CMOS Control bits W2[21] W2[20] W2[19] Acronym Speedy Lock OUT1 OUT0 LOW (0) CMOS output voltage LOW voltage LOW HIGH (1) Speedy Lock mode voltage HIGH voltage HIGH pin #23 pin #24 Comments
In the Speedy Lock mode, the OUT0 and OUT1 pins can be utilized as synchronous switches between active low and a tri-state. The Speedy Lock mode activates the OUT0 and OUT1 pins to be connected to GROUND with a low impedance(< 150) while a high charge pump gain( 8X) is selected and otherwise to a tri-state. For using a programmable CMOS output, the CMOS output bit(W2[21]= LOW) should be activated and then the desired logic level should be programmed with the control bits W2[19] for OUT0 and W2[20] for OUT1.
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FRACTIONAL-N RF/INTEGER-N IF DUAL PLL
S1M8836/37
foLD Control Control Words foLD Control bits W3[21:18] Acronym foLD LOW (0) HIGH (1) Comments Lock Detector (LD), Test mode
select LDs monitoring mode of internal counters.
foLD[3] 0 0 0 0 X X X X 1 1 1 1
foLD[2] 0 0 0 0 1 1 1 1 0 0 0 0
foLD[1] 0 0 1 1 0 0 1 1 0 0 1 1
foLD[0] 0 1 0 1 0 1 0 1 0 1 0 1
foLD Output State Disabled(default LOW) RF and IF Analog Lock Detect Reserved Test Mode Reserved Test Mode Reserved Test Mode IF R Counter Output IF N Counter Output RF R Counter Output RF N Counter Output Reserved Test Mode Reserved Test Mode Reserved Test Mode
When the PLL is locked and the analog lock detect mode is selected, the foLD output is HIGH, with narrow
pulses LOW. Lock Detector(LD) There is analog mode for S1M8836/37. The foLD bits, W3[21:18], are used to select the lock detection mode and to output the selected lock signal through the foLD pin. The foLD output becomes HIGH with narrow pulsed LOW while both RF and IF PLLs are locked and thereby the output should be low-pass filtered for a DC locked voltage HIGH.
23
S1M8836/37
FRACTIONAL-N RF/INTEGER-N IF DUAL PLL
PULSE SWALLOW FUNCTION The RF VCO frequency fVOC becomes NINT + NFRAC times the comparison frequency(fOSC/R) where NINT is the integer divide ratio and NFRAC is the fractional component; fVCO = (NINT + NFRAC) x fOSC/R = N x fOSC/R where NINT = P x B + A RF PLL: NFRAC = F/62976, -31488 F 31488, and R = 1, 2, 3 (typically 2) IF PLL: NFRAC = 0, B > A and 3 R 32767 f VCO: External VCO output frequency f OSC: External reference frequency(From external oscillator) R: Preset divide ratio of programmable R counter (RF: 1, 2, 3(typically 2), IF: 3 to 32767); P: Preset modulus of quadruple modulus prescaler (S1M8836 RF:P=8, S1M8837 RF:P=16, IF:P=8) B: Preset value of main counter (S1M8836/37 RF: 3 to 127, IF: 3 to 4095) A: Preset value of swallow counter division ratio (S1M8836 RF: 0 A 7, S1M8837 RF: 0 A 15. IF: 0 A 7, A24
FRACTIONAL-N RF/INTEGER-N IF DUAL PLL
S1M8836/37
Serial Data Input Timing
MSB DATA DATA[21] DATA[20] DATA[10] DATA[9] CTL[1] LSB CTL[0]
CLOCK tDS LE tDH tDH tCWH tCLE tLEW
OR LE
Phase Detector and Charge Pump Characteristics Phase difference detection Range : -2 to +2 When the positive-slope polarity of PFD is selected, W2[17]=HIGH or W3[13]=HIGH;
fr
fp
LD
CPo
fr > fp
fr = fp
fr < fp
fr < fp
fr < fp
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S1M8836/37
FRACTIONAL-N RF/INTEGER-N IF DUAL PLL
SIMPLIFIED SCHEMATIC DIAGRAM FOR RF SENSITIVITY TEST
2.7V - 4.0V
RF Signal Generator
50 Microstrip 100pF 10dB ATTN 51
VDD fin fin VP 100pF S1M8836/37 LE DATA CLOCK PC Parallel Port 2.2F 100pF 2.2F
100pF OSCin foLD
Frequency Counter
12k 39k
Sensitivity limit is determined when the error of the divided RF output (foLD) becomes 10Hz. fVCO = 1.0GHz, N = 100, P = 8, R = 2 in S1M8836 Integer-N test mode f VCO = 2.1GHz, N = 210, P = 16, R = 2 in S1M8837 Integer-N test mode Typical Application Example
26
FRACTIONAL-N RF/INTEGER-N IF DUAL PLL
S1M8836/37
TYPICAL APPLICATION CIRCUIT
VDD 100pF 0.01F
22 R3 VCO 0.1F RF Out Reference Input 1000pF 51 10pF 100pF Rin 9 OSCin foLD 10 foLD 8 7 6 fin RF 5 fin RF 4 DGND 3 CPORF 2 VPRF 10pF C3 C2 R1 C1
VP 100pF 0.01F VDD 100pF 0.01F
22
1 VDDRF OUT0 24
0.1F
VDDRFa GNDRF
VDD 11 RF_EN OUT1 23
12 IF_EN CLCOK 13 From Controller DATA 14 LE 15 GNDIF 16 finIF 17 fin IF 18 Rin 56pF IF Out 56pF DGND 19 CPOIF 20
VDDIF 22 VPIF 21
0.1F 22 VDD 100pF 0.01F
1000pF
VP . CDMA : UCVA4X103A . K-PCS : UCVW4X102A . US-PCS : UCVA3X120A VCO C13 R13 100pF C12 R11 C11 0.01F
The role of Rin : Rin makes a large portion of VCO output power go to the load rather than the PLL. The value of Rin depends on the VCO power level
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FRACTIONAL-N RF/INTEGER-N IF DUAL PLL
S1M8836/37
PCB LAYOUT GUIDE
In doing PCB layouts for S1M8836/37, we recommend that you apply the following design guide to your handsets, thus improving the phase noise and reference spurious performances of the phones. 1. The S1M8836/37 has external four power supply pins to supply on-chip bias, each for analog and digital blocks of RF and IF PLLs. Basically in doing PCB layout, it is important that power supply lines should be separated from one another and thus coupling noises through the voltage supply lines can be minimized. If you have some troubles with the direction to separate, you can choose the following recommendations for your convenience; * * * Tying analog power lines, VDDRF and VDDIF, is possible. Tying digital power lines, VP1 and VP2, is possible. A point connecting the analog and digital power lines should be near to battery line as close as possible. It minimizes coupling noise effects from a digital switching noise into analog blocks. We also recommend that a passive RC low pass filter(R(22),C(100nF)) be utilized for suppressing high frequency noise on the analog power supply line and reducing any digital noise couplings.
2. VCO power lines should be well separated from those of PLL because VCO is generally a very sensitive device from power line noises and PLL is a digital noise generator. 3. For more improvement of reference spurious performance, it is recommended that the LPF ground be tied to the PLL ground, not the VCO ground.
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FRACTIONAL-N RF/INTEGER-N IF DUAL PLL
S1M8836/37
PACKAGE DIMENSIONS
1.00MAX #1 INDEX AREA 0.27 + 0.05 0.70 + 0.05
4.50 + 0.10
B 3.50 + 0.10 A 0.08 C C
(0.05)
(0.05)
4X0.50 + 0.10 #24 #1
2X4.00
#1 ID MARK
2X 0.10 20X0.50 2X 0.10 C 2X1.00 0.10 M CB CS 24X0.30 + 0.05 C
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